1. Field of the Invention
The invention relates in general to a structure and a fabricating method of a flash memory with a split gate structure. More particularly, this invention relates a flash memory with a split gate structure and having a low erasing voltage and a high erasing speed.
2. Description of the Related Art
In the conventional erasable programmable read only memory (EPROM), a structure similar to an N-type metal oxide semiconductor (NMOS) is formed. A stacked gate comprising a polysilicon floating gate for charge storage and a control gate to control the charge storage is typically applied. Thus, a conventional EPROM has two gates, that is, a floating gate under a control gate. The control gate is connected to a word line, while the floating gate is like a floating island without connecting to another wires or components.
FIG. 1 shows a circuit layout of a conventional flash memory. In a local structure of the memory array, the flash memory on each row has a control gate electrically connected to an identical word line. For example, the control gate G of the flash memory 10 is connected to the word line WL2, while the word line WL1 is connected to the control gate of another row of the memory array. On each column, each flash memory has a source region electrically connected to an identical bit line. For example, the source region S is electrically connected to the bit line BL1, while the drain of each flash memory is electrically connected to another bit line. In this figure, the drain region D on this column is connected to another bit line BL2. Normally, the bit line BL1, the bit line BL2 and the bit line BL3 are distributed in parallel, and perpendicular to the word lines WL1 and WL2 to compose a flash memory array.
In FIG. 2, a schematic drawing of a cross section of a flash memory is shown. On a semiconductor substrate 20, a thin tunnel oxide layer 22 is formed. A floating gate 24 is formed on the tunnel oxide 22. A dielectric layer 26 is formed on the floating gate 24, and a control gate 28 is formed on the dielectric layer 26 to connect an external gate voltage G. In addition, at both sides of the control gate 28 and the floating gate 24, diffusion regions including a source region 30a and a drain region 30b are formed. The source region 30b is connected to an external source voltage S, while the drain region 30a is connected to an external drain voltage D. The drain region 30a is spaced from the floating gate 24 with a distance, that is, a part of a channel region 32 between the drain region 30a and the floating gate 24 is not covered by the floating gate 24, but covered by the control gate 28. Thus, a split gate is formed to have the floating gate 24 and the control gate 28 covering different portions of the channel region 32. The layout of the split gate structure can enhance the operation speed of a flash memory
While programming a flash memory with a split gate, the gate voltage G is high, the source voltage S is high, and the drain voltage D is low. Hot electrons are injected into the floating gate 24. While performing an erasing operation, the tunneling effect occurs between the floating gate 24 and the control gate 28. To reduce the erasing voltage and the increase the erasing speed, a tip is normally formed on the floating gate 24. The conventional method of forming a tip 34 includes using a local oxidation (LOCOS) to form an oxide layer 36 with a bird's beak on the floating gate.
Although the formation of an oxide layer with a bird's beak is advantageous to reduce the erasing voltage and increasing the erasing speed, the wet oxidation method has limitation in reducing linewidth. Therefore, for a highly integrated device, the method can not be applied. In addition, the thermal process used in the local oxidation lowers the thermal budget in the subsequent process, so that the process window is reduced.